112G EPCD Analog Front-End
Architecting the critical voltage translation layer between deep-submicron 5nm digital SerDes and high-voltage silicon photonic modulators. This project encompasses the full IC design lifecycle of a 40 GHz Transimpedance Amplifier (TIA) and a 30 GHz Differential Cascode Driver, engineered for 56 GBaud PAM4 data streams. The core novelty lies in exploiting the transit frequencies of SiGe HBTs to deliver a massive 3V peak-to-peak optical drive swing without sacrificing receiver noise floors.
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